Benoit Steiner http://bsteiner.info/contact.html

Google (Internet related services and products)

Software Engineer, Google Brain (Mountain View, CA)

• More than doubled the speed and scalability of the Google Brain machine learning engine. This resulted in annual savings exceeding $100 million.
• Envisioned, designed, and led the implementation of a high performance framework for numerical computing, on top of which Google Brain has been rewritten. The framework has also been adopted by several other teams for applications such as image processing, recommendation engines, or text understanding.
• Trained a neural network capable of detecting license plates in the StreetView imagery with more than 99.9% accuracy.

Coverity (Source code analysis and verification)

Architect, New Product Initiative (San Francisco, CA)

• Spearheaded the design and implementation of a new product to complement the company's existing product line.
• Developed the first prototypes and used them as vehicles for demonstrations. Leveraged off-the-shelf solutions such as Mahout for quick experimentations.
• Wrote the functional specification for the final product and participated in its implementation.
• Managed the relationship with the project external partner in Japan.

Tabula (Programmable logic design)

Technical Lead and Senior Software Manager, Infrastructure (Santa Clara, CA)

• Led and grew to 6 people the team developing the infrastructure software upon which the company relies to program its semiconductor chips (code generators, device and design databases, bit stream generator, timing analysis engines, clock router, and so on...).
• Tackled cross functional projects such as reducing the power consumption of the device, optimizing the memory footprint of the software, or leveraging distributed computing to speed up the generation of device models.
• Personally designed and implemented an innovative approach to compute the fastest frequency at which a chip can operate.
• Pioneered the use of contractors located in Eastern Europe as a flexible and cost efficient way to increase the QA bandwidth when needed.

Magma Design Automation (Software tools for semiconductor design)

Senior Manager, Formal Verification (San Jose, CA)

• Led the development of a new tool that automatically finds several classes of bugs in a semiconductor design.
• Started the project from the ground up. Assembled, trained and coached a small but highly technical team. Worked with the marketing department and potential customers to define the initial requirements and roadmap.
• Acted as architect, technical lead and individual contributor. Sketched the overall architecture including the custom high performance database. Designed and implemented the property checking engine that formed the heart of the tool.

Senior Manager, Timing Analysis (Santa Clara, CA)

• Managed an international team of more than 10 people responsible for the incremental timing analysis engine used to predict the frequency at which semiconductor chips operate.
• Led major new developments: rewrote the tool to leverage multiple CPUs for speed, made use of statistical models to capture the electrical variability of the transistors, etc...
• Incrementally increased the tool accuracy and expanded its reporting capabilities. Held brainstorming sessions to identify technical solutions, scheduled their implementation, drove (and often personally tackled) the development, and ensured final customer adoption by integrating the feedback received during early beta testing engagements.
• Continuously improved the overall quality of the tool: decreased the runtime by up to 4 orders of magnitude on some very large designs, dramatically reduced the bug filing rate, fixed several design flaws, enforced more stringent code reviews, etc...

Monterey Design Systems (CAD software for semiconductor design)

Technical Lead, R&D (Mountain View, CA)

• Started as an intern before being hired as a software developer in July 2001 and eventually became the technical lead of the timing analysis team in 2003.
• Increased the scalability of the timing analysis tool by reducing the computational complexity of several algorithms and by leveraging up to 32 threads to perform the computations. Designed and developed new capabilities required to take into account the impact of manufacturing process variations on the performance of the chip.
• Trained team members and helped them develop new solutions to existing problems and dramatically reduce the memory footprint of the tool.

Ensim (Internet infrastructure solutions for hosting providers)

Intern, Internet Application Network division (Sunnyvale, CA)

• Designed, developed and debugged software for managing licensing and billing.
• Adapted HP's OpenMail mail server to Ensim's "hosting ready" platform.

Mycom International (GSM network design and monitoring)

Intern, software development division (London, UK)

• Developed a powerful HTML generator and a Web based software interface.
• Improved the speed and robustness of the database connectivity engine.

Peregrine Systems (Corporate asset and infrastructure management)

Intern, product development department (Bourg La Reine, France)

• Developed an SNMP agent used for remote resource management.
• Designed and implemented efficient template trees in C++.